Semiconductor manufacturers produce semiconductor wafers having hundreds or even thousands of integrated circuits (ICs, also known as chips or semiconductor devices) per wafer. As device geometries decrease and the size of semiconductor wafers increases, the time needed to test all the ICs on semiconductor wafers has increased. This issue is important for testing memory chips where the time to test a chip increases with increases in chip capacity. As a result, memory manufacturers have been driven to test an ever larger number of chips in parallel. Consequently, wafer level testing has become a widely accepted method for testing memory ICs on 200 mm diameter wafers, and is progressing rapidly to full wafer testing for 300 mm diameter wafers. However, industry movement toward full wafer testing has been hindered by difficulty in making good and reliable electrical contact with all chips on a wafer simultaneously. Further, such difficulty is exacerbated at high temperatures by thermal expansion and warpage of the wafer.
In wafer level testing, a number of test probes are placed in contact with selected regions of a wafer under test and, for each die, probe tips are contacted to each bonding pad thereon. Then, using computer controlled test equipment, voltages are generated and conducted to the probe tips, thereby testing a certain number of ICs on the wafer. Typically, wafer level testing involves testing each die to determine whether it passes basic electrical tests such as a test for electrical opens or electrical shorts. In some applications, a functional test is also performed to ensure that the ICs perform as designed.
As the number of elements of an IC to be tested increases (along with an increase in the number of ICs on a wafer), the total number of probe tips contacting a wafer produces a large increase in net force loading of probe tips against the wafer. As a result, under load, a probe substrate warps so much that in some high density applications, deflection of the probe substrate due to warping approaches the displacement range of the probe tips themselves. As a consequence, probe tips do not make uniform or reliable contact with ICs on a wafer under test.
Various approaches to reduce warping under load have been tried with limited success. In one approach, a probe substrate is divided into an array of probe substrate tiles. Each substrate tile may be supported on a number of posts to distribute the load more evenly across the wafer surface and to alleviate warping of the probe substrate tile. A further refinement uses active feedback systems to adjust the heights of the posts to reduce warping effects. While dividing the probe substrate into smaller substrate tiles helps to reduce warping, the tiled probe head introduces a new set of problems including leveling of each probe substrate tile to form a coplanar surface of probe tips, and accurately registering each probe substrate tile with respect to adjacent probe substrate tiles.
Testing high reliability semiconductor devices is often done at several different temperatures to find defects that may cause failure in operation under extreme thermal conditions. For example, DRAM memory devices are tested at temperatures as high as 125° C., and more recently, at even higher temperatures. At such high temperatures, probe substrates and support structures distort and warp, making it difficult to maintain planarity of test probes and to maintain registration of each probe in an X and a Y direction within a plane of the probes. Various approaches to alleviate warping and mis-registration due to testing at high temperature have been proposed. In several approaches, a probe substrate is divided into an array of probe substrate tiles. Each substrate tile may be supported on flexible posts, actuators, invar matrices, and so forth. Notwithstanding these efforts, probe heads for full wafer testing at high temperatures are not satisfactory. Wafer probe heads often need to be re-leveled at high temperature to compensate for thermal distortion caused by raising the temperature of the probe head and the wafer under test.
As the number of contact probes on a probe head increases, the head is more difficult to manufacture, repair and align because of yield loss and complexity. Dividing the probe head into an array of probe substrate tiles alleviates problems with fabrication yield and assembly at the expense of additional alignment requirements. In a probe head made up of an array of probe substrate tiles, each probe substrate tile must be registered and leveled with respect to adjacent substrate tiles. Time and expense of registering and leveling the probe head increases with the number of probe substrate tiles making up the probe head.